The present invention relates to a manufacturing method of a thin film transistor array substrate for a liquid crystal display and more particularly, it relates to a manufacturing method of an active matrix type of liquid crystal display (referred to as an LCD, hereinafter) using a thin film transistor (referred to as a TFT, hereinafter) as a switching element. More specifically, it relates to a manufacturing method of an active matrix type of liquid crystal display (TFT-LCD) using a TFT array substrate having fewer point defect and display uniformity, which is formed by four or five photolithography processes so as to have its display characteristics and productivity improved in a case where a low electric resistance wiring material is used as a gate wiring material and a source wiring material.
An electric optical element for a display using liquid crystal is increasingly applied to a product making use of a characteristic in which it is thin and power consumption is low, as a flat panel display instead of a CRT.
There are a passive matrix-type liquid crystal display and a TET-LCD using the TFT as a switching element, as an electric optical element for display using liquid crystal. The TFT-LCD having characteristic superior to the passive matrix-type liquid crystal display in view of portability and visual quality has largely come into practical use for a notebook computer and the like. In the TFT-LCD, a liquid crystal layer is sandwiched between a TFT array substrate and an counter substrate in general. The TFT is formed in the shape of an array on the TET array substrate. Polarization plates are provided outside of the TFT array substrate and the counter substrate, and a backlight is provided outside of the substrate. In such constitution, preferably a color display is provided.
However, in the TFT-LCD, it is necessary to manufacture the TFT array substrate on which the TFT is formed in the shape of an array on a glass substrate using a semiconductor process technique, while various kinds of defects such as breaking of a wiring, short circuit between wirings or the like are likely to occur because of a pattern defect generated in the actual manufacturing process to cause a yield to be lowered and a manufacturing cost is increased because the number of devices required for manufacturing is increased.
As a method of solving the above problems, for example, Japanese Unexamined Patent Publication No. 10-268353 discloses a manufacturing method of an active matrix-type liquid crystal display in which a TFT array substrate is formed by five photolithography processes. In addition, Japanese Unexamined Patent Publication No. 250958/2001, Japanese Unexamined Patent Publication No. 339072/2001, Japanese Unexamined Patent Publication No. 26333/2002 and Japanese Unexamined Patent Publication No. 59939/2003 disclose an active matrix-type liquid crystal display in which a TFT array substrate is formed by four photolithography processes. Japanese Unexamined Patent Publication No. 339072/2001, Japanese Unexamined Patent Publication No. 26333/2002 and Japanese Unexamined Patent Publication No. 59939/2003 disclose a method of forming photo resist patterns having different film thickness by multiplex exposure using halftone mask.
FIGS. 11 to 13 are explanatory views showing an essential part of the conventional TFT array substrate disclosed in Japanese Unexamined Patent Publication No. 59939/2003, in which elements on an insulating substrate (not shown) are shown. FIG. 11 is a plane view, FIG. 12 is a sectional view schematically showing a sectional structure taken along line A-A in FIG. 11, and FIG. 13 is a view schematically showing a sectional structure of a terminal part for connecting a TCP (Tape Carrier Package) provided outside of a display region. The TOP connects a signal potential source which supplies a signal potential to be input to a gate wiring, a source wiring, a subsidiary capacitor wiring and a common electrode of an counter substrate, to the gate wiring, the source wiring, the subsidiary capacitor wiring and the common electrode, respectively.
Referring to FIGS. 11 to 13, reference numeral 1 designates a gate electrode, reference numeral 2 (not shown) designates a subsidiary capacitor electrode, reference numeral 3 designates a gate insulating film, reference numeral 4 designates a semiconductor film, reference numeral 5 designates an ohmic contact film, reference numeral 6 designates a drain electrode, reference numeral 7 designates a source electrode, reference numeral 8 designates an interlayer insulating film, reference numeral 9 designate a pixel contact hole, reference numeral 11 designates a pixel electrode, reference numeral 13 designates a gate terminal electrode, reference numeral 14 designates a gate terminal contact hole serving as a first contact hole, reference numeral 20 designates a subsidiary capacitor wiring, reference numeral 21 designates a gate wiring, reference numeral 22 designates a source wiring, reference numeral 23 designates a part of the ohmic contact film 5 shown on the plane view.
The gate electrode 1 is an electrode which is a part of the gate wiring 21, or a terminal branching off from the gate wiring 21 to be connected to each TFT. Referring to FIG. 11, the part designated by reference numeral 23 has upper and lower two-layer structure of the ohmic contact film 5 and the semiconductor film 4 in FIG. 12.
According to the manufacturing method in which the TFT array substrate is formed by four photolithography processes disclosed in the prior art, since the source wiring 22 and the source electrode 7 do not climb over bumps of the semiconductor film and the ohmic contact film 23 in the display, breaking of the source wiring 22 and the source electrode 7 caused by the bumps of the semiconductor active film and the ohmic contact film 23 can be prevented, and since the patterns of the source electrode and the drain electrode are included in a semiconductor pattern so that they do not cross each other, a leak current can be also kept low. In addition, according to Japanese Unexamined Patent Publication No. 10-268353, although a semiconductor active film and an ohmic contact film 23 are left in the vicinity of a pixel electrode 11, since the pixel electrode 11 is separated from the semiconductor film, the ohmic contact film 23 and a source wiring 22 at an interlayer insulating film 8, a simple short circuit between the source wiring 22 and the pixel electrode 11 caused by pattern defects of the semiconductor film, the ohmic contact film 23 and the source wiring 22, or a short circuit when resistance of the semiconductor film 4 is lowered under irradiation of light can be eliminated.
Meanwhile, in a field of the TFT-LCD, it is demanded that electric resistance of a wiring material is lowered to avoid accordingly increasing wiring electric resistance because of trends for a wiring length to be increased and a width of a wiring to be reduced, which are accompanied by trends of increasing a panel size and fine pixel size for TV or monitor of recent years. As wiring materials conventionally used in general, there are titanium (Ti), chrome (Cr), tantalum (Ta), tungsten (W) and an alloy mainly containing these. Among the above, Cr which can be processed in a relatively easy manner by wet etching having high productivity, and shows a low resistance value and high corrosion resistance, has been used widely. However, aluminum (Al), molybdenum (Mo) and an alloy of these having specific electric existence further lower than the above are preferably being used for the future.
However, in the conventional TFT array substrate constitution disclosed in Japanese Unexamined Patent Publication No. 10-268353, when an Al film is used for a metal thin film material of the gate wiring 21 and the source wiring 22 as a low electric resistance wiring, small projections called hillocks are generated on the Al film surface by heating and an interlayer insulation defect is generated. In addition, an oxide layer is formed between the gate wiring 21 and the source wiring 22, and the electrically connected pixel electrode 11, and contact electric resistance at the connection parts of the gate wiring 21/the pixel electrode 11 and the source wiring 22/the pixel electrode 11 is increased so that a display visual defect is generated. Furthermore, when the Al film is used for the metal thin film material of the source wiring 22, contact electric resistance at a connection part between the source wiring 22 and the ohmic contact film 23 electrically connected thereto is increased, so that a display defect is generated.
Still further, when a Mo film is used for a metal thin film material of the gate wiring 21 or the source wiring 22, although contact electric resistance with the pixel electrode 11 and contact electric resistance with the ohmic contact film 23 is preferable, there is a problem that water corrosion resistance is low and reliability is lowered, or a problem that the Mo film is excessively etched during a dry etching process for forming the pixel contact hole 9 in the interlayer insulating film 8 and a contact defect is generated because there is no Mo film at a contact hole opening. Still further, when a multilayer laminated structure combining Al and Mo is provided to compensate for the defects of the Al film and the Mo film, when Al is etched using a chemical agent containing well-known phosphoric acid and nitric acid group, since the laminated Mo layer is excessively etched away, the etching process cannot be performed, which is a serious problem.
In other words, it is substantially impossible to implement the TFT-LCD in which low resistance metal such as Al or Mo is used as it is for the wiring material by the above manufacturing method.